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Features
* * * * * * * * * *
Eight DSPs and 24-bit Audio Router On-chip 32 kHz to 96 kHz Sampling Rate 16-bit Microcontroller On-chip Variety of I/Os, including SmartMediaTM and DataFlash(R) Embedded RAM for Single Chip Operation (768 Kbits) Warm Start Power-down 1A Typical Deep Power-down, 0.5 mW/MIPS Typical Operating External Flash/ROM Capability Available in a 100-lead TQFP Package Ideal for Real-time Audio Applications - Wavetable Synthesis - MP3 Decoding - Effect Processing (Reverb, Echo, Chorus, Equalizer) - Filtering, Sampling Rate Conversion * Typical Applications: Karaoke, Professional Audio, Cellular Phones, Musical Instruments, Consumer Electronics
Audio Processing ATSAM3308 Combined MIDI-Synthesizer and MP3 Decoder
Description
The ATSAM3308 is a member of the new ATSAM3000 family that uses the DSP array technology. The ATSAM3308 includes eight 24-bit DSPs, a 24-bit Audio Router and a general-purpose 16-bit on-chip CISC microcontroller. Its high performance and flexibility with 8-input/8-output channels enables implementation of audio applications in professional-quality sound production such as MP3 decoding with time stretch and pitch control, concurrent Wavetable synthesis, effect processing and digital mixing. A variety of I/Os, including external Wave ROM, SmartMedia(R) and DataFlash(R) are provided. Sampling rates up to 96 kHz at 24 bits are supported.
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DSP Array Block Diagram
Figure 1. ATSAM3308 DSP Array Block Diagram
DSP Array (8 P24 DSPs)
External RAM ROM Flash
Embedded RAM 16k x 24
MMU
Sync Bus
Async Bus
16 bit Processor (P16)
I/Os, Timers, UARTs, DataFlash, Ports
Router Final ACC MIX Audio OUT Audio IN
Audio I/0
Embedded ROM 1k x 16 BIOS and Debug External I/O
ATSAM3308
Functional Description
DSP Array
The ATSAM3308 includes eight on-chip DSPs. Each DSP (P24) is built around a 2k x 24 RAM and a 1k x 24 ROM. The RAM contains both data and P24 instructions, the ROM contains typical coefficients such as FFT cosines and windowing. A P24 sends and receives audio samples through the Sync Bus. It can request external data such as compressed audio through the Async Bus. Each P24 RAM can be accessed through the Async Bus. Each P24 is capable of typical MAC operation loops, including auto-indexing, bit reverse and butterfly (multiplication of complex numbers). It also includes specialized audio instructions such as state variable IIR filtering, envelope generation, linear interpolation and wavetable loop. One P24 is sufficient for processing one channel of MP3 data pump, implementing a multi-tap delay line or a multi-tap transversal filter. A single P24 is also capable of generating twelve voices of wavetable sound at 32 kHz sampling rate (8 voices at 48 kHz), including sample cache, pitch control, 2nd order filter and two envelope generators.
Sync Bus
The Sync Bus transfers data on a frame basis, typical frame rates being 32, 44.1, 48 or 96 kHz. Each frame is divided into 64 time slots. Each slot is divided into 4 bus cycles. Each P24 is assigned a hardwired time slot (8 to 63), during which it may provide 24-bit data to the bus (up to 4 data samples). Each P24 can read data on the bus at any time,
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allowing inter P24 communication at the current sampling rate. Slots 0 to 7 are reserved for a specific router DSP, which also handles audio out, audio in, and remix send.
Async Bus
The Async Bus has 24-bit data inside the chip and 16-bit data outside. The P16 processor normally masters the Async Bus; it can read/write the P24 memories and the external or embedded ROM/RAM. However, each P24 can request a bus master cycle for accessing external ROM/RAM or other P24 memories. This allows efficient intercommunication between several P24s on asynchronous block basis. Specific P24 instructions FLOAT and FIX convert fixed-point DSP data to floating-point 16 bits. This allows for 20-bit audio dynamic range when using 16-bit external memory.
16-bit Processor
The P16 processor is widely used in ATSAM products. Using the P16 keeps large firmware investments from the ATSAM97xx series. A built-in ROM, connected to the P16 holds basic input/output software (BIOS) for peripherals such as UART, DataFlash, SmartMedia and MPU, as well as a debugger that uses a dedicated asynchronous serial line. The firmware can reside on external parallel ROM/Flash or it can be downloaded at power-up into the built-in 16k x 24 RAM from serial EEPROM, DataFlash, SmartMedia or host. The MMU handles transfer requests between the external or embedded RAM/ROM, the P16 and the P24s through the Async Bus. The ATSAM3308 includes 16k x 24 RAM on chip. This block includes RAM (accessed through the Async Bus) that defines the routing from the Sync Bus to/from the Audio I/O or back to the Sync Bus (mix send). It takes care of mix and accumulation from Sync Bus samples. Eight channels of audio in and eight channels of audio out are provided (4-stereo in/out, I2S format). The stereo audio in channels may have a different sampling rate than the audio out channels. In this case, one (or more) P24 takes care of sampling rate conversion. The ATSAM3308 includes very versatile I/Os, that share common pins for reduced pin count and small IC footprint. Most I/Os, when not used for a specific function, remain available as firmware controlled general-purpose pins. The following peripherals are included on chip: * * * * * * * * 2 x 8-bit timers 2 x 16-bit timers Parallel slave 8-bit port, MPU401 compatible Parallel master 8-bit port, for connection to SmartMedia and/or LCD display, switches, etc. 2 x asynchronous bidirectional serial ports Synchronous serial slave port (SPI type host connection). SPI master bidirectional port for EEPROM or DataFlash connection. Firmware controlled I/O pins.
MMU (Memory Management Unit) Router: Final ACC, MIX, Audio Out, Audio In
I/O
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Typical Application Examples
Host-controlled MP3 + High Quality Wavetable Player
Figure 2. Host-controlled MP3 + High Quality Wavetable Player
ROM Compressed Audio and MidiFile (from host) ATSAM33308 DAC ADC
Stereo Audio In/Out
* * *
Concurrent MP3 + wavetable Legendary Dream high quality wavetable sound Typical polyphony: - - 56 voices with effects (reverb, chorus, etc.) @48 kHz sampling rate MP3 decode + 32 voices with effects @48 kHz sampling rate
* *
External wavetable ROM/Flash choice from 4 Mbits to 128 Mbits Choice of host communication interfaces - - - 8-bit parallel Asynchronous serial (MIDI) Synchronous serial (SPI)
*
Built-in Standard Midi file player (SMF) dramatically reduces host load
Musical Keyboard with Key Velocity
Figure 3. Musical Keyboard with Key Velocity
Keyboard
ROM Switches, LCD Display MIDI ATSAM3308 DAC ADC
Stereo Audio In/Out
* * *
Up to 64-voice polyphony with effects Choice of GM+ sampled sounds from 4 Mbits to 64 Mbits Maximum external memory addressing range: 128 Mbits
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DSP Capacity and I/O Configuration
DSP Considerations
The ATSAM3308 includes 8 x P24 DSPs. Table 1 below lists the performance achievable by the P24. Table 1. P24 Performance
Function MP3 decode 12-voice wavetable synthesis @32 kHz 8-voice wavetable synthesis @48 kHz Stereo reverb and chorus @48 kHz Stereo 31-band equalizer @48 kHz P24s Required 3 1 1 1 3
The ATSAM3308 runs firmware directly from an external ROM/Flash memory. It may also run firmware from local RAM, thus freeing many I/O pins, which can then be used for application dependent functions. The ATSAM3308 is the ideal choice when wavetable synthesis or many I/O pins are required.
I/O Selection Considerations
Host-controlled Operation
I/Os are organized in groups, which can be mutually exclusive because they share the same IC pins (please refer to the pinout to identify the exclusions). The two main types of operation are host controlled and stand-alone. There are three main possible ways of communication with a host processor: * * * 8-bit parallel MPU type bidirectional interface signals: D7 - D0, CS, WR, RD, A0, IRQ Asynchronous serial, MIDI_IN and optionally MIDI_OUT Synchronous serial signals: SDIN, SCLK, SYNC, INT
Stand-alone Operation
Possible stand-alone modes are: * * * Firmware into external ROM or Flash memory Firmware into external EEPROM or DataFlash Firmware into external SmartMedia. In this case, the firmware should reside in the SmartMedia reserved sectors starting at sector # 1.
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Pinout
Pin Description
In the Pin Description table below: * * * Table 2. Pinout by Pin Name
Pin Name GND VC18 VC33 PWRIN PWROUT D7 - D0 Pin Number 9, 22, 30, 41, 56, 70, 75, 87, 97 20, 47, 73, 99 13, 50, 83 29 28 96, 95, 91, 90, 82, 81, 77, 76 96, 95, 91, 90, 82, 81, 77, 76 96, 95, 91, 90, 82, 81, 77, 76 96, 95, 91, 90 Type PWR PWR PWR PWR PWR I/O Sharing Description - - - - - 1 Digital ground. All of these pins should be returned to a ground plane. Core power. All of these pins should be returned to nominal 1.8V or to PWROUT if the built-in power switch is used. Periphery power. All these pins should be returned to nominal 3.3V. Power switch input; should be returned to nominal 1.8V even if the power switch is not used. Power switch output; should be connected to all VC18 pins if the power switch is used Slave 8-bit interface data. Output if CS and RD are low (read from chip), input if CS and WR are low (write to chip). Type of data defined by A0 input. SmartMedia data or other peripheral data General-purpose I/O; can be programmed individually as input or output. Optional bit clocks for digital audio input. Used for sampling rate conversion for external incoming digital audio such as AES/BEU or S/Pdif. Optional word selects for digital audio input. Used for sampling rate conversion for external incoming digital audio such as AES/BEU or S/Pdif. Slave 8-bit interface address. Indicates data/status or data/ctrl transfer type (CS/RD, low or CS/WR low) SmartMedia presence detect General-purpose input pin Serial slave synchronous interface input clock Slave 8-bit interface chip select, active low. General-purpose input pin Serial slave synchronous interface input sync signal Slave 8-bit interface write, active low. D7 - D0 data is sampled by chip on WR rising edge if CS is low SmartMedia configuration. This pin is sensed after power-up. If found low, it is assumed that a SmartMedia connector is present. The built-in firmware will wait for SmartMedia SMPD. General-purpose input pin
Identical sharing number indicates multifunction pins. Pd indicates a pin with built-in pull-down resistor. Pu indicates a pin with built-in pull-up resistor.
I/O7 - I/O0 P0.7 - P0.0 CLAD3 - 0
I/O I/O In
1 1 1
WSAD3 - 0
82, 81, 77, 76
In
1
A0 SMPD P0.10 SCLK CS P0.11 SYNC WR SMC
98 98 98 98 100 100 100 1 1
In In In In In In In In In
2 2 2 2 3 3 3 4 4
P0.12
1
In
4
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Table 2. Pinout by Pin Name (Continued)
Pin Name RD R|B P0.13 IRQ SMRE FS0 P0.8 INT MIDI_IN P0.14 SDIN MIDI_OUT FS1 Pin Number 2 2 2 8 8 8 8 8 17 17 17 18 18 Type In In In Out Out In I/O Out In In In Out In Sharing Description 5 5 5 6 6 6 6 6 7 7 7 8 8 Slave 8-bit interface read, active low. D7 - D0 data is output when RD goes low and CS is low SmartMedia Ready Busy/ status General-purpose input pin Slave 8-bit interface interrupt request. High when data is ready to be transferred from chip to host. Reset by a read from host (CS = 0 and RD = 0) SmartMedia read enable (RE), active low Frequency sense, sensed at power up. Together with FS1, allows the firmware to know the operating frequency of the chip (see FS1). General-purpose I/O pin Serial slave synchronous interface data request, active low. Serial MIDI in General-purpose input pin Serial slave synchronous interface input data Serial MIDI out Frequency sense, sensed at power up. FS1/FS0 allow firmware to know operating frequency of chip as follows: 00 6.9552 MHz 01 9.6 MHz 10 11.2896 MHz 11 12.288 MHz General-purpose I/O Four stereo channels of digital audio output, I2S format Audio bit clock for DABD3 - 0. Audio bit clock for DAAD3 - 0 if the corresponding CLAD3 - 0 is not used. Audio left/right channel select for DABD3 - 0. Audio left/right channel for DAAD3 - 0 if the corresponding WSAD3 - 0 is not used. External DAC/Codec master clock. Same frequency as X2 pin. Can be programmed to be 128xFs, 192xFs, 256xFs, 384xFs, where Fs is the DAC/Codec sampling rate. Stereo audio data input, I2S format. Can operate on CLBD master rate or CLAD0 external rate when sampling rate conversion is requested. General-purpose input pin Three additional channels of stereo audio input, I2S format. Can individually operate on CLBD master rate or corresponding CLAD3 - 1 when sampling rate conversion is requested. DAAD3 - 1 have built-in pull-downs. They may be left open if not used. External DAC/Codec Mute. Sensed at power up. If found high, then MUTE becomes an active high output. If found low, then MUTE becomes an active low output. General-purpose I/O pin External memory address bit, extension to 64 Mbits
P0.9 DABD3 - 0 CLBD WSBD CKOUT
18 67, 66, 65, 64 6 7 5
I/O Out Out Out Out
8 -
DAAD0 P0.15 DAAD3 - 1
54 54 60, 59, 55
In In In Pd
9 9 -
MUTE
19
I/O
10
P1.6 WA21
19 45
I/O Out
10 11
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Table 2. Pinout by Pin Name (Continued)
Pin Name SMCE P1.5 WA20 SMALE P1.4 WA19 SMWE P1.3 WA18 SMCLE P1.2 WA17 - WA16 P1.1 - P1.0 WA15 - WA0 Pin Number 45 45 44 44 44 43 43 43 42 42 42 58, 57 58, 57 53, 51, 40, 39, 38, 37, 36, 27, 26, 21, 16, 15, 14, 12, 11, 10 53, 51, 40, 39, 38, 37, 36, 27, 26, 21, 16, 15, 14, 12, 11, 10 94, 93, 92, 89, 88, 86, 85, 84, 80, 79, 78, 69, 68, 63, 62, 61 94, 93, 92, 89, 88, 86, 85, 84, 80, 79, 78, 69, 68, 63, 62, 61 3 3 4 4 48 48 49 49 23 25 32 24 Type Out I/O Out Out I/O Out Out I/O Out Out I/O Out I/O Out Sharing Description 11 11 12 12 12 13 13 13 14 14 14 15 15 16 SmartMedia chip enable (CE), active low General-purpose I/O pin External memory address bit, extension to 32 Mbits SmartMedia address latch enable (ALE) General-purpose I/O pin External memory address bit, extension to 16 Mbits SmartMedia write enable (WE), active low General-purpose I/O pin External memory address bit, extension to 8 Mbits SmartMedia command latch enable (CLE) General-purpose I/O pin External memory address bits, extension to 2 and 4 Mbits General-purpose I/O pins External memory address bits, up to 1 MBits (64K x 16)
P2.15 - P2.0
I/O
16
General-purpose I/O pins
WD15 - WD0
I/O
17
External memory data
P3.15 - P3.0
I/O
17
General-purpose I/O pins
WCS1 P1.10 WCS0 P1.9 WOE P1.8 WWE P1.7 DFCS DFSI DFSO DFSCK
Out I/O Out I/O Out I/O Out I/O Out Out In Pd Out
18 18 19 19 20 20 21 21 -
External memory chip select 1, active low. Pre-decode for an external RAM/Flash/ROM at address 200:0000H. General-purpose I/O pin External memory chip select 2, active low. Pre-decode for an external RAM/Flash/ROM at address 000:0000H General-purpose I/O pin External memory output enable, active low General-purpose I/O pin External memory write enable, active low General-purpose I/O pin DataFlash chip select DataFlash serial input (to DataFlash) DataFlash serial output (from DataFlash). This pin has a built-in pulldown. It may be left open if not used. DataFlash data clock
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Table 2. Pinout by Pin Name (Continued)
Pin Name P1.15 X1 - X2 Pin Number 46 72,71 Type I/O Pu Sharing Description General-purpose I/O pin. This pin has built-in pull-up. It may be left open if not used. External crystal connection. Standard frequencies are 6.9552 MHz, 9.6 MHz, 11.2896 MHz, 12.288 MHz. Max frequency is 12.5 MHz. An external clock (max. 1.8 VPP) can be connected to X1 using AC coupling (22 pF). A built-in PLL multiplies the clock frequency by 4 for internal use. PLL decoupling RCR filter Master reset Schmitt trigger input, active low. RESET should be held low during at least 5 ms after power is applied. On the rising edge of RESET, the chip enters an initialization routine, which may involve firmware download from an external SmartMedia, DataFlash or host. Serial test input. This is a 57.6 Kbaud asynchronous input used for firmware debugging. This pin is tested at power-up. The built-in debugger starts if STIN is found high. STIN has a built-in pull-down. It should be grounded or left open for normal operation. Serial test output. 57.6 Kbaud async output used for firmware debugging. Power down input, active low. High level on this pin is typ. VC18. When PDWN is low, the oscillator and PLL are stopped, the power switch opens, and the chip enters a deep sleep mode (1 A typ. consumption when power switch is used). To exit from power down, PDWN has to be set high then RESET applied. Alternate programmable power-downs are available which allow warm restart of the chip. Test input. Should be grounded or left open.
LFT RESET
74 33
In
-
STIN
34
In Pd
-
STOUT PDWN
35 31
Out In
-
TEST
52
In Pd
-
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Pinout by Pin Number
Table 3. ATSAM3308 Pinout by Pin Number
Pin # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 WR SMC P0.12 RD R|B P0.13 WCS1 P1.10 WCS0 P1.9 CKOUT CLBD WSBD IRQ GND WA0 P2.0 WA1 P2.1 WA2 P2.2 VC3 WA3 P2.3 WA4 P2.4 WA5 P2.5 MIDI_IN P0.14 SDIN MIDI_OUT FS1 P0.9 MUTE P1.6 VC18 WA6 P2.6 GND DFCS DFSCK DFSI Pin # Pin Name 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 WA7 P2.7 WA8 P2.8 PWROUT PWRIN GND PDWN DFSO RESET STIN STOUT WA9 P2.9 WA10 P2.10 WA11 P2.11 WA12 P2.12 WA13 P2.13 GND WA18 SMCLE P1.2 WA19 SMWE P1.3 WA20 SMALE P1.4 WA21 SMCE P1.5 P1.15 VC18 WOE P1.8 WWE P1.7 VC33 Pin # Pin Name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 WA14 P2.14 TEST WA15 P2.15 DAAD0 P0.15 DAAD1 GND WA16 P1.0 WA17 P1.1 DAAD2 DAAD3 WD0 P3.0 WD1 P3.1 WD2 P3.2 DABD0 DABD1 DABD2 DABD3 WD3 P3.3 WD4 P3.4 GND X2 X1 VC18 LFT GND Pin # Pin Name 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 D0 I/O0 P0.0 WSAD0 D1 I/O1 P0.1 WSAD1 WD5 P3.5 WD6 P3.6 WD7 P3.7 D2 I/O2 P0.2 WSAD2 D3 I/O3 P0.3 WSAD3 VC33 WD8 P3.8 WD9 P3.9 WD10 P3.10 GND WD11 P3.11 WD12 P3.12 D4 I/O4 P0.4 CLAD0 D5 I/O5 P0.5 CLAD1 WD13 P3.13 WD14 P3.14 WD15 P3.15 D6 I/O6 P0.6 CLAD2 D7 I/O7 P0.7 CLAD3 GND A0 SMPD P0.10 SCLK VC18 CS P0.11 SYNC
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Mechanical Dimensions
Figure 4. Thin Plastic 100-lead Quad Flat Pack (TQFP100B)
Table 4. Package Dimensions in mm
Denomination A A1 A2 L D D1 E E1 P B 0.13 Min 1.40 0.05 1.35 0.45 Nom 1.50 0.10 1.40 0.60 14.00 12.00 14.00 12.00 0.40 0.18 0.23 Max 1.60 0.15 1.45 0.75
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Electrical Characteristics
Absolute Maximum Ratings (*)
Ambient Temperature (power applied)................-40C to 85C Storage Temperature ........................................-65C to 150C Voltage on any pin X1, LFT ....................................................... -0.3 to VC18 + 0.3V Others ......................................................... -0.3 to VC33 + 0.3V Supply Voltage.......................................................................... VC18 ....................................................................-0.3V to 1.95V VC3 .......................................................................-0.3V to 3.6V Maximum IOL per I/O pin................................................. 4 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Table 5. Recommended Operating Conditions
Symbol VC18 VC33 PWRIN TA Note: Parameter Supply voltage Supply voltage
(1)
Min 1.65 3 1.75 0
Typ 1.8 3.3 1.9 -
Max 1.95 VC18 + 1.5 3.6 1.95 70
Unit V V V C
Supply voltage PWRIN pin Operating ambient temperature
1. Operation at lower VC33 values down to VC18 is possible, however external timing may be impaired. Contact Atmel in case of use of these circuits with VC33 outside the recommended operating range.
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DC Characteristics
Table 6. DC Characteristics (T A = 25C, VC18 =1.8V 10%, VC33 = 3.3V 10%)
Symbol VIL VIH VIH VOL VOH ICC1 ICC2 ICC3 Parameter Low level input voltage High level input voltage, except X1, PDWN High level input voltage X1, PDWN Low level output voltage IOL = -2 mA High level output voltage IOH = 2 mA VC18 power supply current (crystal freq.=11.2896 MHz, all 8 P24s running) VC18 power supply current (crystal freq. = 11.2896 MHz, all P24s stopped) VC18 power supply current (crystal freq. = 11.2896 MHz, all P24 stopped, warm start powerdown active) VC18 deep power down supply current (using power switch) Built-in pull-up/pull-down resistor Min -0.3 2.3 1.2 2.9 Typ 63 22 4 Max 1.0 VC33 + 0.3 VC18 + 0.3 0.4 Unit V V V V V mA mA mA
ICC4 PU/PD
10
1 -
10 56
A k
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Peripherals and Timings
8-bit Slave Parallel Interface
Timings The Slave Parallel Interface is typically used to connect the chip to a host processor. Pins used: D7 - D0 (I/O), A0 (Input), WR (Input), RD (Input), IRQ (Output). Figure 5. Host Interface Read Cycle
A0 t AVCS CS t CSLRDL RD t DWS D0 - D7 t DWH t PRD t RDHCSH
Figure 6. Host Interface Write Cycle
A0 t AVCS CS t CSLWRL RD t DWS D0-D7 t DWH t PWR t WRHCSH
Table 7. Timing Parameters
Symbol tAVCS tCSLRDL tRDHCSH tPRD tRDLDV tDRH tCSLRWRL tWRHCSH tPWR tDWS tDWH Parameter Address valid to chip select low Chip select low to RD low RD high to CS high RD pulse width Data out valid from RD Data out hold from RD Chip select low to WR low WR high to CS high WR pulse width Write data setup time Write data hold time Min 0 5 5 50 5 5 5 50 10 0 Typ Max 20 10 Unit ns ns ns ns ns ns ns ns ns ns ns
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IO Status Register
7 TE 6 RF 5 X 4 X 3 X 2 X 1 X 0 X
Status register is read when A0 = 1, RD = 0, CS = 0. * TE: Transmit Empty If 0, data from ATSAM3308 to host is pending and IRQ is high. Reading the data at A0 = 0 will set TE to 1 and clear IRQ. * RF: Receiver full. If 0, then ATSAM3308 is ready to accept DATA from host.
Note: If status bit RF is not checked by host, write cycle time should not be lower than 3 s.
SmartMedia and Other Peripheral Interfaces
The SmartMedia and Other Peripheral Interface is a master 8-bit parallel interface that provides connection to SmartMedia or other peripherals such as LCD screens. Pins used: I/O7 - I/O0 (I/O), SMPD (input) SMCE, SMALE, SMCLE, SMRE, SMWE (outputs) All of these pins are fully under firmware control, therefore timing compatibility is ensured by firmware only.
EEPROM/DataFlash Interface
The EEPROM/DataFlash interface is a master synchronous serial interface, operating in SPI mode 0. Pins used: DFCS, DFSI, DFSCK (outputs), DFSO (input) The DFSCK frequency is firmware programmable from fck to fck/64, where fck is the crystal frequency. Thus a large variety of EEPROM/DataFlash devices can be accomodated. Please refer to Atmel DataFlash datasheets for accurate SPI mode 0 timing. Figure 7. DataFlash Interface Typical Timing
DFS CK
DFSI
LSB
DFSO
MSB
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Serial Slave Synchronous Interface
The ATSAM3308 can be controlled by an external host processor through this unidirectional serial interface. However, no firmware can be downloaded at power-up through this interface. Therefore an external ROM/Flash/EEPROM is required. Pins used: SCLK, SYNC, SDIN (input) INT (output) Data is shifted into MSB first. The IC samples an incoming SDIN bit on the rising edge of SCLK, therefore the host should change SDIN on the negative SCLK edge. SYNC allows initial synchronization. The rising edge of SYNC, which should occur with SCLK low, indicates that SDIN will hold MSB data on the next rising SCLK. The data is stored internally into a 256 byte FIFO. When the FIFO count is below 64, the INT output goes low. This allows the host processor to send data in burst mode. The maximum SCLK frequency is fck (fck being the crystal frequency).The minimum time between two bytes is 64 fck periods. The contents of the SDIN data are defined by the firmware. Figure 8. Serial Slave Interface Typical Timing
SCLK
SYNC
SDIN
MSB
Digital Audio
Pins used: CLBD (output), WSBD (output) DABD3 - 0 (outputs) DAAD3 - 0 (inputs) Optionally: CLAD3 - 0 (inputs), WSAD3 - 0 (inputs) The ATSAM3308 allows for 8 digital audio output channels and 8 digital audio input channels. All audio channels are normally synchronized on single clocks CLBD, WSBD which are derived from the IC crystal oscillator. However, as a firmware option, the DAAD3 - 0 inputs can be synchronized with incoming CLAD3 - 0 and WSAD3 - 0 signals. In this case, the incoming sampling frequencies must be lower or equal to the chip sampling frequency. The digital audio timing follows the I2S standard, with up to 24 bits per sample Figure 9. Digital Audio Timing
tCW WSB tCW tCLBD
CLB tSOD DABD3 - 0 DAAD3 - 0 tSOD
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Table 8. Digital Audio Timing Parameters
Symbol tCW tSOD tCLBD Parameter CLBD rising to WSBD change DABD valid prior/after CLBD rising CLBD cycle time Min tC - 10 tC - 10 Typ 2 * tC Max Unit ns ns ns
tC is related to tCK, the crystal period at X1 as follows: Table 9. Sample Frequency Sample Frequency
WSBD 1/(tCK * 128) 1/(tCK * 192) 1/(tCK * 256) 1/(tCK * 384) Typical Sample Frequency 96 kHz 64 kHz 48 kHz 32 kHz tC tCK 2 * tCK 2 * tCK 4 * tCK CLBD/WSBD Frequency Ratio 64 48 64 48
The choice of sample frequency is done by firmware. Figure 10. Digital Audio Frame Format,128 x Fs and 256 x Fs Modes
WSB
CLDB
DABD3 - 0 DAAD3 - 0 MSB LSB (16 bits) LSB (24 bits) MSB
Figure 11. 192 x Fs and 384 x Fs Modes
WSB
CLDB
DABD3 - 0 DAAD3 - 0 MSB LSB (16 bits) LSB (24 bits) MSB
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Serial MIDI_IN and MIDI_OUT
The serial MIDI IN and OUT signals are asynchronous signals following the MIDI transmission standard: * * Baud rate: 31.25 kHz Format: start, 8 data bits, 1 stop
External Memory
Pins used: WA21 - WA0 (address out), WD15 - WD0 (data bi-directional) WCS0, WCS1 (pre-decodes out) WOE (output enable) WWE (write) When using all address bits, the maximum addressing range is two pages (WCS0, WCS1) of 4M words (total = 16 Mbytes). Figure 12. ROM/Flash Read Cycle
tRC WCS0 WCS1 tCSOE
WA0 - WA21 tPOE WOE tOE WD0 - WD15 tACE tDF
Table 10. External Memory Parameters
Symbol tRC tCSOE tPOE tACE tOE tDF Note: Parameter Read cycle time Chip select low/address valid to WOE low Output enable pulse width Chip select/address access time Output enable access time Chip select or WOE high to input data Hi-Z Min 5 * pLCK 2 * pLCK - 5 5 * pLCK - 5 3 * pLCK - 5 0 Typ 3 * pLCK Max 6 * pLCK 3 * pLCK + 5 2 * pLCK-5 Unit ns ns ns ns ns ns
1. A built-in PLL multiplies the crystal clock frequency by 4 for internal use. pLCK is the period of the internal clock generated by PLL. pLCK = tCK/4. Typical value with crystal 12.288 MHz is pLCK = 20 ns. 2. Memory access time should be lower than tACE min. Typical value with crystal 12.288 MHz is 90 ns.
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Figure 13. External RAM/Flash Write Timing
tWC WCS0 WCS1 tCSWE WA0 - WA21
WOE tWP WWE tDW WD0 - WD15 tDH
Table 11. External Flash Timing Parameters
Symbol tWC tCSWE tWP tDW tDH Parameter Write cycle time Write enable low from CS or Address or WOE Write pulse width Data out setup time Data out hold time Min 5 * pLCK 2 * pLCK - 10 4 * pLCK - 10 10 Typ 4 * pLCK Max 6 * pLCK Unit ns ns ns ns ns
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Reset and Powerdown
During power up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which takes max. 10 ms. After the low to high transition of RESET, the following happens: * * * * * All P24s enter an idle state. P16 program execution starts in built-in ROM. STIN is sensed. If HIGH, then the built-in debugger is started. Addresses 0 & 1 from external ROM are checked. If "DR" is read, then control is transferred to address 400H from external ROM. SMC is sensed. If LOW, then the built-in loader waits for SmartMedia presence detect (SMPD). When detected, the firmware is down loaded from SmartMedia reserved sector 1 and started. An attempt is made to read the first two bytes of an external EEPROM or DataFlash. If "DR" is read, then the built-in loader loads the firmware from the external EEPROM/DataFlash and starts it. Firmware download from a host processor is assumed.
The power-up sequence is as follows:
*
*
1. The 0ACh byte is written to the host, this raises IRQ. The host can recognize that the chip is ready to accept program download. Higher speed transfer can be reached by polling the parallel interface status (CS = 0, A0 = 1, RD = 0). 2. The host sends the firmware size (in words) on two bytes (Low byte first). 3. The host sends the ATSAM3308 firmware. The firmware should begin with string "DR". 4. The 0ACh byte is written to the host, this raises IRQ. The host can recognize that the chip has accepted the firmware. 5. ATSAM3308 starts the firmware. If PDWN is asserted low, then the crystal oscillator and PLL will be stopped. If the power switch is used, then the chip enters a deep power down sleep mode, as power is removed from the core. To exit power down, PDWN has to be asserted high, then RESET applied. Other power reduction features allowing warm restart are controlled by firmware: * * P24s can be individually stopped. The clock frequency can be internally divided by 256.
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Recommended Board Layout
Like all HCMOS high integration ICs, following simple rules of board layout is mandatory for reliable operations: * GND, VC33, VC18 distribution, decoupling All GND, VC33, VC18 pins should be connected. A GND plane is strongly recommended. The board GND + VC33 distribution should be in grid form. Recommended VC18 decoupling is 0.1 F at each corner of the IC with an additional 10 F decoupling close to the crystal. VC33 requires a single 0.1 F decoupling. * Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-CR and the IC should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from the IC. * Buses Parallel layout from D0 - D7 and WA0 - WA21/WD0 - WD15 should be avoided. The D0 - D7 bus is an asynchronous type bus. Even on short distances, it can induce pulses on WA0 - WA21/WD0 - WD15 which can corrupt address and/or data on these buses. A ground plane should be implemented below the D0 - D7 bus that connects both to the host and to the IC GND. A ground plane should be implemented below the WA0 - WA21/WD0 - WD15 bus that connects both to the ROM/Flash grounds and to the IC. * Analog Section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the analog section.
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Recommended Crystal Compensation and LFT Filter
Figure 14. Recommended Crystal Compensation and LFT Filter
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Product Development and Debugging
Atmel provides an integrated product development and debugging tool SamVS. SamVS runs under Windows(R) (98, ME, 2000, XP). Within the environment, it is possible to: * * * * Edit Assemble Debug on real target (In-circuit Emulation) Program Flash, Dataflash, EEPROM, SmartMedia on target.
Two dedicated IC pins, STIN and STOUT allow running firmware directly into the target using standard PC COM port communication at 57.6 Kbauds. Thus time-to-market is optimized by testing directly on the final prototype. A library of frequently used functions is available, such as: * * * * * Wavetable synthesis Reverb/Chorus MP3 decode 31-band equalizer Parametric equalizer
Atmel engineers are available to study customer-specific applications.
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(c) Atmel Corporation 2004. All rights reserved. Atmel (R) and combinations thereof, Dream (R) and DataFlash(R) are the registered trademarks of Atmel Corporation or its subsidiaries. Windows(R) 98, Windows(R) 2000, Windows(R) ME and Windows(R) XP are the registered trademarks of Microsoft Corporation. SmartMedia TMis the trademark of SanDisk Corporation, MPEG Layer-3 audio decoding technology licensed from Fraunhofer and Thomson Multimedia. Other terms and product names may be the trademarks of others. Printed on recycled paper.
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